1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit connected to a lead electrode through a bonding wire.
2. Description of the Related Art
A currently available IC chip includes a core region having a logic circuit and a memory circuit, and an I/O region provided in a periphery of the core region. The I/O region is provided with a bonding pad for connecting the IC chip and a lead electrode provided on a lead frame side. There is known a technology in which, along with the progress of a miniaturization technology for semiconductor integrated circuits, the I/O region is made smaller (see JP2007-305822A and JP2007-059867A, for example).
JP 2007-305822 A describes a technology relating to a semiconductor integrated circuit, in which shortage of connection pads for supplying power to a core region is prevented so that the same connection method can be applied to all the connection pads without decreasing a cell width of an I/O cell. In the technology described in JP 2007-305822 A, two rows of connection pads are arranged with shifts on I/O cells of an I/O region, and connection pads are also arranged on core power wiring arranged along a side of the core region. Each pad pitch among those connection pads is set, with respect to a cell pitch of the I/O cells, as pad pitch=2×cell pitch, and a pad pitch of the whole connection pads is set as pad pitch/3(=2×cell pitch/3), whereby three connection pads are arranged per two I/O cells.
Further, JP 2007-059867 A describes a technology for reducing an area of a semiconductor integrated circuit by reducing in size of an I/O region. In the technology described in JP 2007-059867 A, an interlayer film is provided on an entire surface of the semiconductor integrated circuit while keeping a state in which a part of a pad metal formed on the I/O region is exposed. Further, an electrode pad is provided on the interlayer film of an active region (core region). The pad metal and the electrode pad are electrically connected to each other through a connection via. Then, a protective film is formed on the entire surface of the semiconductor integrated circuit with the electrode pad being exposed. JP2007-059867A discloses a technology of, with such a structure, making the I/O region smaller than the electrode pad.
In response to the miniaturization of devices along with the progress of the semiconductor technology, the I/O cell of the I/O region has also been miniaturized. In contrast to the miniaturization of the I/O cell, a bonding pad is difficult to be made small, and hence a region occupied by the bonding pad may become a cause that hinders reduction in size of the entire IC chip.